Nilesh Vighe
Principle Engineer @Cadence
- Role
- Principal Engineer at Cadence
- Location
- Pune District, MH, IN
- LinkedIn followers
- 500 followers
About Nilesh Vighe
10 plus years of experience in fullchip/block level Floor planning/Integration, Power/Bump plan, RDL routing Fullchip/IP ESD planning and verification, Reliability verification, Extraction, fullchip timing,Analog layout design, Physical verification, in 7nm(TSMC/Intel),10 nm 14nm nodes.
Experience
Principal Engineer
Jun 2023 — Present · Pune, IN
Education
Savitribai Phule Pune University
Bachelor of Science (B.Sc.), Electronics science
2009 — 2010
Pune University
Master of Science (M.Sc.) VLSI, Electronic Science
2011 — 2012
S.S.G.M.College, Kopargaon
H.S.C, Physics; Chemistry; Mathematics and Biology
2007
Skills
- Vlsi
- Verilog
- Lvs
- Cadence Virtuoso
- Semiconductors
- Physical Design
- Tcl
- Vhdl
- Asic
- C
- Soc
- Drc
- Very-Large-Scale Integration (Vlsi)
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