Nikunj Hinsu
- Role
- Soc Design Engineer - Verification Validation at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Nikunj Hinsu
Total Experience: 10 years 4+ years of experience in SoC & ASIC Subsystem Design…
Experience
Soc Design Engineer - Verification Validation
May 2021 — Present
Currently working on Full Chip Scalable Coherent Fabric Verification in Intel Server SoCs. Previously Worked on Pre-Silicon Design Verification/Validation of Cache Coherency IP present within next generation Intel CPUs & SOCs (System-on-Chips). This role further involves exposure to following- Cache Coherence Protocols like MESI - SystemVerilog Testbench (SVTB)- OVM (UVM)- Unit Testing - Integrated Development Environment (IDE) Tools like DVT Eclipse - Agile practices like SCRUM - Developing post-processing checkers using Python/Pycharm - Revision Control Tools like GIT - and lot more other techniques and challenges….
Skills
- Sata
- Cortex
- Vlsi
- Tcl
- Universal Verification Methodology (Uvm)
- Verilog
- Very-Large-Scale Integration (Vlsi)
- Oop
- Vhdl
- Open Verification Methodology (Ovm)
- C
- Formal Verification
- Matlab
- Ncsim
- Perl Script
- Javascript
- Mipi
- Asic
- Amba Ahb
- Java
- Systemverilog
- Embedded Systems
- I2c
- Cadence Schematic Capture
- C++
- Eclipse
- Linux
- Uvm
- Programming
- Software Development
- Perl
- Functional Verification
- Simvision
- Core Java
- Application-Specific Integrated Circuits (Asic)
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