Nikhil Surdi
Senior Principal Design Engineer
- Role
- Senior Principal Design Engineer at Cadence
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
About Nikhil Surdi
A VLSI design engineer with a Master\'s degree and 9+ years of experience in the semiconductor industry. Experience includes defining the specifications, architecture, micro-architecture, integration and RTL design for networking SoC and IPs like Ethernet PCS, RS & Firecode FECs, Interlaken, USB and PCI Express. Worked as design engineer for HBM(DDR) and NAND Flash (ONFI, Toggle) memory protocols which includes FPGA design and validation.I am a coding enthusiast. Learned PERL for automation and learned VBA for mathematical modelling of the FECs and analyzing impact of various IP configurations on latency & gate count. Also learning Chisel (A Scala based HDL) through online courses.
Experience
Senior Principal Design Engineer
Nov 2025 — Present · Pune, IN
Education
Indian Institute of Technology, Bombay
Master of Technology (M.Tech.), Electronic systems
2008 — 2011
Maharashtra Institute of Technology
B.E., Electronics and Tele-communication
2004 — 2008
Skills
- Verilog
- Pcie
- Semiconductors
- Toggle
- Nand Flash
- Microelectronics
- Rtl Design
- Vlsi
- Static Timing Analysis
- Asic
- Logic Synthesis
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