Nikhil Prabhu

About Nikhil Prabhu

I am pursuing Masters of Science in Electrical Engineering at San Jose State University and specializing in Digital Logic Design. I also have a keen interest in Digital Signal Processing (DSP) and Communications-> In-depth knowledge on Digital Logic Design, Static Timing Analysis (STA), CMOS Integrated Circuits-> Good Understanding of Physical Design Flow (Floorplanning, Clock Tree Synthesis, place and Route)-> Comprehensive Understanding of Computer Architecture Concepts (Pipelining, Cache Memory, Virtual Memory and Tomasulo Algorithm)-> Hands-on experience of complex algorithm implementations on Xilinx and Altera FPGA Boards-> Proficient in Python scripting using regular expressions and hashes-> 3 years of academic experience in RTL Simulation, Logic Synthesis, Static Timing Analysis,Gate-level Simulation, Power Analysis & Optimization. TECHNICAL SKILLS-> Programming & Scripting Languages: Python (Scripting), Verilog (RTL), SystemVerilog, C++-> EDA Tools: Synopsys: VCS, Design Compiler, Cadence: Virtuoso, Encounter, Spectra Simulator, NCSim, Xilinx ISE, Xilinx Vivado, Altera Quartus II, Modelsim 10.3c-> Synthesis & Simulation Tools: Design Complier, NC Verilog, MATLAB-> Hardware proficiency: Oscilloscope, Spectrum Analyzer, Logic Analyzer, Network Analyzer-> Operating System: Unix, iOS, Windows-> Bus Protocols: UART, AMBA – APB and AHB, PCIe.Other skills include DFT methodologies like SCAN and BIST for evaluating chip level faults.

Experience

1. R & d Engineer, Sr Staff

   Synopsys Inc

   Feb 2025 — Present · San Francisco, CA, US

   Developing Interface solutions for HAPS

Education

• University of Mumbai

  Bachelor’s Degree, Electrical, Electronics and Communications Engineering

  2009 — 2013

• San José State University

  Master's Degree, Electrical and Electronics Engineering

  2014 — 2016

Skills

• Xilinx Ise
• Matlab
• Modelsim
• Digital Signal Processing
• System Generator
• C++
• C
• Verilog
• Field-Programmable Gate Arrays (Fpga)
• Systemverilog
• Software Defined Radio
• Python
• Fpga
• Asic
• Rtl Design
• Static Timing Analysis
• Simulink
• Microsoft Office
• Vlsi
• Gnu Radio