Nikhil Karkare

About Nikhil Karkare

Semiconductor professional with over 12 years of experience in ASIC/SoC DFT domain:• Hands-on experience in planning and implementing DFT solutions for SoC blocks for networking domain across multiple 40nm/28nm/16nm/7nm/5nm/4nm/3nm projects.• Hands-on experience of SCAN tests implementation using LogicBIST, EDT, SSN- ATPG, DRC, coverage analysis, test points insertion, low power techniques• Memory BIST implementation with knowledge of memory repair techniques• Boundary Scan implementation• Integration of DFT ready IPs and verification• Test patterns generation - SCAN, MBIST, BSCAN• Test patterns verification and debug in timing/no-timing scenarios • Silicon bring-up & post-silicon activities- Full chip production patterns delivery- Post-silicon debug support- Diagnosis and yield improvement through pattern optimization- Memory repair• Design Fixes for DFT (ECOs) using Synopsys Design compiler.• Exposure to timing constraints and STA, LEC.• Fair knowledge of standards (IJTAG).• Perl, TCL, shell, flow automation techniques.• Experienced in interacting/collaborating with cross-domain teams.

Experience

1. Senior Silicon Dft Engineer

   Google

   Nov 2023 — Present · Bengaluru, IN

Education

• Indian Institute of Technology, Bombay

  Master of Technology (M.Tech.), Microelectronics

  2010 — 2013

• Vishwakarma Institute Of Technology

  Bachelor of Engineering (BE), Electronics and Telecommunication

  2006 — 2010

Skills

• Joint Test Action Group (Jtag)
• Automatic Test Pattern Generation (Atpg)
• Microcontrollers
• Perl
• Embedded Systems
• Eda
• System on a Chip (Soc)
• Matlab
• Low-Power Design
• C
• Microsoft Office
• Vlsi
• Testing
• Memory Bist
• Static Timing Analysis
• Synopsys Tools
• Vhdl
• Simulations
• Debugging
• Silicon
• Asic
• Bist
• Linux
• Mentor Graphics
• Application-Specific Integrated Circuits (Asic)
• Tcl
• Verilog
• Pspice
• Logic Bist
• Labview
• Dft
• Simulink
• Electronics