Nijesh C
Principal Physical Design Engineer
- Role
- Principal Engineer at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Nijesh C
Working @Intel GPU team as RLS SD micro-arch tech lead. Drove multiple floorplan path finding and RLS Convergence planning for GPGPUs. Nijesh lead 1st GPGPU Foveros Convergence planning. Expertise in Foveros Design SD implementation and micro-arch planning. SD expert for GPGPU L3cache & Node fabric Convergence. Nijesh has Implemented multiple micro-arch optimization for RLS Convergence simplification and CDYN optimizations along with RTL Design Architects. He has wider work experience in multiple roles as partition execution owner, section floorplan owner, Section STA owner, full chip FP lead, Section lead, GPU routing Convergence lead with Foveros design, L3cache/ L3node/3D FP & RLS path finding lead, Fullchip timing Convergence lead, GPU RLS Convergence Tech lead etc.
Experience
Principal Engineer
Aug 2025 — Present · Bengaluru, IN
PD Technical convergence lead for SOC peripherals includes HBM, D2D, Tlie2Tile logic, Infra, PLL, GPIO, NOC IPs
Education
Indian Institute of Technology, Delhi
Master of Technology - MTech, Integrated Circuit Design
2008 — 2010
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