Nidhi S.

About Nidhi S.

Experienced Semiconductor Professional with 13+ years of experience in Design for Test Domain.Key Responsibilities:* DFT Architecture definition and implementation (65nm to 5nm SOC)* Test-mode Clocking Module Design, DRC Cleanup and STA constraint Signoff* Methodology improvements/automation across technology nodes* Low power Scan implementation and pattern generation* Memory BIST implementation, repair and Failure analysis * RTL level DFT implementation and Verification* Zero Delay and Timing based(SDF) Simulations and debug* Silicon Bring up and Post Silicon activities on ATE, Production support at customer\'s end* Good understanding of 1500, IJTAG and industry-standard Fault models* Mentoring and leading a group of engineers through SOC Design CycleSpecialties:*MemoryBist, ATPG based scan design.*Silicon Bringup, Debug and FailureAnalysis.*Logic Design and Verification.*Test mode clock design and timing analysisTool Skils:*Tessent Hybrid flow (TK+LBIST), Tessent/LV MBIST flow*Tessent Yield Assist & Silicon Insight*NCSim, VCS, Verdi*Synopsys DC, DFTAdvisor, Primetime, Spyglass*TCL, PERL, Python & Shell Scripting

Experience

1. Ic Design Engineer

   Broadcom

   Jan 2012 — Present

Education

• Motilal Nehru National Institute Of Technology

  B.Tech

  2004 — 2008

Skills

• Mixed Signal
• Application-Specific Integrated Circuits (Asic)
• Ic
• Debugging
• Silicon
• Tcl
• Systemverilog
• Atpg
• Very-Large-Scale Integration (Vlsi)
• Hardware Architecture
• Vlsi
• Jtag
• Rtl Design
• Primetime
• Amba Ahb
• Dft
• Vhdl
• Simulations
• Functional Verification
• Verilog
• Asic
• Bist
• Low-Power Design
• Modelsim
• Formal Verification
• Logic Design
• Automatic Test Pattern Generation (Atpg)
• Integrated Circuits (Ic)
• Ncsim