Nidhin George
Design Verification Engineer at UST
- Role
- Design Verification Engineer at UST
- Location
- Kottayam, KL, IN
- LinkedIn followers
- 500 followers
About Nidhin George
Success depend on how you learn, not on when you learn.\"Verilog | System Verilog | Universal Verification Methodology | Assertion Based Verification using SVAFSM based design | Simulation Code | Coverage Functional Coverage Synthesis | Static Timing Analysis (STA)| RTL Coding | Digital electronics | Digital design | Mentor Graphics-Questasim | Intel-Quartus Prime Lite | ModelSimLinux | WindowsThe strong desire to start career in Semiconductor Industry for which I am getting trained in VLSI course. The willing to work in a challenging position with a growing organization where I can utilize my technical and interpersonal skills and enhance the same.
Experience
Design Verification Engineer
Apr 2024 — Present · Bengaluru, IN
Education
Amal Jyothi College of Engineering
Bachelor of Technology - BTech
2015 — 2019
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