Nidhin Chandran
Design Verification Engineer | Verilog | SystemVerilog | UVM | ECE CUSAT ’24
- Role
- Asic Design Engineer at Netrasemi
- Location
- Thiruvananthapuram, KL, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Nidhin Chandran
I am a VLSI Design and Verification Engineer, graduate in Electronics and Communication…
Experience
Asic Design Engineer
Aug 2025 — Present
Education
ST Mary's HSS Edoor
SSLC
Cochin University of Science and Technology
Bachelor of Technology - BTech
2020 — 2024
GHSS Aralam
PLUS TWO
2018 — 2020
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