Nick Tabing

About Nick Tabing

n••••••••@gmail.com- Full-stack developer, specialized in React, JavaScript, Java and MongoDB-Verilog RTL design and UVM/OVM verification-AR/VR display-SoC Security-NVMe VIP implementer-PCIe and SSD NVMe verification-4G/5G RF Front-end verification-Video codec RTL design and verification-Neural network & machine learning-IPTV platform development-Test-plan formulation-VIP implementation-Regression automation/debug-Data storage improvement-Gate-level simulation-Python scripting.Professional Skills: Hardware Design and Verification skills: RTL, Gate-Level Simulation, interface modeling, transactor modeling, static timing analysis, Verilog and System Verilog, running CAD flows on synthesis. Regression triage, input/output throttle testing, debug, assertions in the unit level, direct and random tests, reference models.Hardware verification methodologies: UVM/OVM. Design documentation: Block and timing diagrams, testing documentation, transaction flow. Video compression standards: AVS, JPEG, MPEG4-2, H264 (SVC and AVC), H265. Hardware skills: PCIe, NMVe, AXI, VHDL, Verilog, System Verilog, VCS, Verdi, Spyglass, FPGA, Ncverilog, SimVision. ModelSim, DVE, Debussy, CMOS, MIPI RFFE, Assembly Language, Neural Network, Machine Learning.Software skills: C/C++, Java, Python, HTML, JavaScript, CSS, Angular, React, NPM, Selenium.Project Management: Success providing results-oriented, full life cycle project management by leading expert component and design engineering and product development teams in local, domestic, and international long and short term projects. Excel at creating innovative component solutions and propelling project development. Repeated success delivering projects on time and on budget.Award Winning: Recognized by Intel Corporation for contributions and commitment to building Intel’s Consumer Electronics business via DHG’s first production IA SoC orders. Recognized again by Intel for the Consumer Products Engineering Operational Excellence Award for delivering AVS for GVL.

Experience

1. Senior Design Verification Engineer

   Amazon

   Oct 2022 — Present · Redmond, WA, US

   Pre-silicon verification of networking SoC subsystems including SystemVerilog/UVM environments, firmware-driven testing, FPGA integration and scalable verification infrastructure.• Developed SystemVerilog/UVM environments for networking SoC subsystems • Implemented firmware-driven verification using embedded CPUs • Built SerDes protocol verification infrastructure supporting Ethernet and IPv4

Education

• University of Illinois Urbana-Champaign

  Bachelor, Computer Engineering

  2004 — 2008

Skills

• Product Management
• Rtl Development
• Vhdl
• Simulations
• Code Coverage
• Software Engineering
• Processors
• Video Processing
• Formal Verification
• Transactors
• Vmm
• Algorithms
• Project Management
• Semiconductors
• Linux
• Unix
• Perl
• Embedded Systems
• Pcie
• Ovm
• Vlsi
• C
• Programming
• Documentation
• Debugging
• Regression Analysis
• Synthesis
• Systemverilog
• Timing Diagrams
• Matlab
• Random Tests
• Rtl Design
• Direct Tests
• Universal Verification Methodology (Uvm)
• Digital Signal Processors
• C++
• Fpga
• Video Codec
• Computer Science
• Rtl Verification