Neha Bhoraskar

About Neha Bhoraskar

Hands-on technical leader, working with cross-functional teams to influence tools, flows and PV methodology for faster, efficient and accurate to spec design for next generation Intel SoCs.10+ years of experience on multiple cutting-edge CPU projects (Core i3, i5, i7) in all aspects of physical design from technical readiness to final sign off prior to project tape-in. In-depth understanding of all aspects of Timing flow, physical construction, integration and physical verification.The responsibilities in back-end physical design included initial feasibility studies, placement, floor-planning, high-speed circuit design, clock design, cross-voltage and cross-clock design convergence, noise, power analysis and convergence, and final layout cleanup.Led/co-owned Timing sign-off for multiple features like Memory Controller, DDRPHY, PCIE, Integrated Graphics, Core, AI IPs and SoC. Thorough knowledge of SDC constraints management. Collaborated closely with RTL and Physical Design team for timing constraint validation. Experience on design of highly complex, digital functional blocks for PV (timing, power and noise) convergence, layout and formal equivalence verification. Participated in physical design (Synthesis, Place and Route) methodology discussions and custom recipes to achieve power efficient high-performance designs.Worked closely with block owners for timing correlation studies between Place and Route Designs (Fusion, Fusion Sign-off) and PrimeTime. Successfully enabled Hyperscale context for faster turn-around in timing ECO loops. Generated and implemented ECOs to fixing timing, signal integrity.Document and guidelines/specs for IP teams with respect to floorplan, PV scenarios for timing closure, design-specific constraints.

Experience

1. Soc Sta Engineer

   Rivos Inc

   Sep 2025 — Present

Education

• Savitribai Phule Pune University

  Be, Engineering

  2002 — 2006