Maxim Nefedov
Asic Design Engineer @Synopsys Inc
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WORK HISTORY
Asic Design Engineer @Synopsys Inc
Responsibilities:• Design and developing ASIC RTL for PCI Express controller IP. • Analyzing and optimizing design performance, power, and area metrics.
EDUCATION
Southwest State University (SWSU)
Master's degree, Automation and Control
Southwest State University (SWSU)
Master’s engineering degree in "Mechatronics"
ABOUT MAXIM NEFEDOV
Experienced engineer, specializing in the design of digital IP cores for ASIC/FPGA and embedded systems. Advanced RTL design using Verilog, SystemVerilog, VHDL RTL sign-off: linting, CDC, RDC, timing constraints, functional verification, equivalence checks PPA optimization based on synthesis and power estimation CAD tools: Synopsys Design Compiler, Spyglass, Verdi, Formality, Cadence Xcelium, Simvision FPGA prototyping Xilinx UltraScale+, Virtex, Vivado, Vitis HLS, Altera Agilex, Stratix10, Quartus Embedded hardware and software co-design across SoC, FPGA and MCU using C/C++ DSP/ML algorithm research using MATLAB/Simulink, Python and optimization for efficiency for target hardware FPGA/ASIC
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