Neeti Shah
- Role
- Soc Design Engineer at Apple
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Neeti Shah
Self driven and detail oriented project lead with a track record of delivering projects…
Experience
Soc Design Engineer
May 2017 — Present
Successfully taped out multiple complex chips as physical verification lead - Led schedules and supported cross functional engineering effort - Performed various types of physical verification checks (DRC, LVS, ERC, ANT, DFM) at the chip and block level - Integrated full chip driving physical verification convergence with high focus on interfaces - Collaborated with CAD, technology and sign-off teams for flow bring up and validation - Worked on padring, bump, RDL design working closely with package and floorplan teams
Skills
- Keil
- Fpga
- Linux
- Java
- Modelsim
- Microsoft Excel
- Systemc
- Computer-Aided Design (Cad)
- Cadence Virtuoso
- Vlsi
- Tcl
- C++
- Microsoft Word
- C
- Perl
- Python
- Microsoft Office
- Html
- Computer Architecture
- Windows
- Altera Quartus
- Powerpoint
- Verilog
- Digital Circuit Design
- Xilinx
- Vhdl
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