Neeraj Purohit

About Neeraj Purohit

Analog Circuit design Engineer: 1. Working on PLL - Micro-architecture of PLL - Behavioral modelling - VCO design - Charge pump - Phase frequency detector (PFD)- AC coupled level shifter design - Top level PLL loop simulations2. Designed low power LDO for full chip in 45nm TSMC3. Designed LDO for PLL in 14nm FinFET GF process4. Receiver design for high speed DDR3/4 and LPDDR3/4 interfaces- PreAmp - Continuous time linear equalizer - High speed level shifter - Duty cycle corrector circuit - High speed Sampler- DAC (digital to analog converter) 5. Designed Strobe gating circuit for DDR3/4; Drift tracking circuit to track drift between incoming strobe signal from DRAM 6. Worked on High bandwidth memory (HBM) receiverUnderstands: PLL loop dynamics, DDR3/4 architecture, DDR3/4 and LPDDR3/4 signalling (SSTL,PODL, HSUL, LVSTL ), HBM (high bandwidth memory) architectureHands on experience in 7nm FinFET GF, 14nm FinFET GF LPP, 28nm GF HPP and 45nm TSMC processes.

Experience

1. Senior Staff Engineer Manager

   Qualcomm

   Dec 2024 — Present

   Manager, Analog and RFIC design

Education

• Indian Institute of Science (IISc)

  Master of Technology (MTech), Electronic Systems Engineering

  2012 — 2014

Skills

• Fpga
• Electronics
• Digital Electronics
• Very-Large-Scale Integration (Vlsi)
• Signal Processing
• Mixed Signal
• Circuit Design
• Embedded Systems
• Field-Programmable Gate Arrays (Fpga)
• Vlsi
• Verilog
• Pspice
• C++
• Matlab
• C
• Xilinx
• Analog and Mixed Signal Vlsi Circuit Design
• Vhdl
• Analog
• Labview
• Microcontrollers