Neeraja Kumari Pathak
Physical Design Engineer at Analog Devices | Ex- Intel | Ex- Qualcomm
- Role
- Lead Physical Design Engineer at Analog Devices
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Neeraja Kumari Pathak
Strong fundamentals in Physical Design execution through handling diverse blocks inmultiple projects (18A, 4nm, 5nm, 8nm, 14nm etc).• Expertise includes floor-planning, PnR, timing closure, physical verification (PV) clean-up,meeting PDN requirement, working on CLP fixes and resolving FV issues.• Implemented blocks with different complexities such as millions of instances, thousands offeed throughs, multiple power domains etc.• RTL to GDS for multiple blocks with various macros, power domains, higher frequency, etc.• Floorplan for blocks with multiple power domains, feedthroughs, analog and digital IPs, highmacro count, etc.• PnR execution for multiple TILES - blocks from floorplan to GDS with power, performanceand area optimization.• Participated in block closure in various signoff domains delivering the best quality.• Support and debug in methodology development.• Handling multiple blocks in a single project.• Leading other blocks.• Mentoring Juniors and Knowledge Transfer to lateral entries.• Cross team communication and engagement.• Successfully completed several tape-outs under fast paced design environment with toughdeadlines.• EDA Tools: Synopsys - Fusion Compiler (FC), Cadence - Innovus.
Experience
Lead Physical Design Engineer
Nov 2025 — Present
Education
Manipal School of Information Sciences
Master of Engineering - MEng
Visvesvaraya Technological University
Bachelor of Engineering
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