Neeraj Sharma

Senior Principal Application Engineer (Emulation) at Cadence Design Systems

Role
Senior Principal Application Engineer at Cadence
Location
Austin, TX, US
LinkedIn followers
500 followers
Information TechnologyView LinkedIn profile

About Neeraj Sharma

With over 15 years of experience in Emulation, ASIC prototyping, Pre-silicon validation, Post-silicon validation, FPGA Design, and RTL Design, I am a highly motivated engineer who is passionate about my work. My expertise includes designing and implementing a unified environment for Pre-Post silicon validation, strong experience with HW-assisted methodologies, developing numerous Synthesizable benches, BFMs, and transactors IP\'s for use in emulation, and integrating emulation platforms with real targets such as PCIe speed bridge, Ethernet speed bridge, and USB Speed bridges. Additionally, I have rich experience in SoC integration and leading tape out efforts of multiple chips, and I am skilled in HDL/Programming Languages like Verilog, VHDL, System Verilog and scripting languages like TCL, Shell.

Experience

  1. Senior Principal Application Engineer

    Cadence

    Nov 2017 — Present · Austin, TX, US

    As an application engineer, I have worked with prominent semiconductor clients in North America and India, supporting multiple emulation flows for designing multi-billion-gate systems. My primary responsibilities have included providing comprehensive support for emulation platforms, specifically Palladium and Protium. This has involved understanding customer requirements and suggesting appropriate emulation flows, while also striving to enhance compile time and run time performance. I have developed methodologies and emulation environments for both customer and in-house use, and conducted training sessions to help engineers gain a better understanding of the Palladium and Protium platforms.

Education

  • Centre for Development of Advanced Computing (C-DAC)

    PG Dimpola in VLSI, VLSI

    2008 — 2008

  • Himachal Pradesh University

    B.Tech., Electronics and Communications

    2003 — 2007

Skills

  • Verilog
  • Rtl Design
  • Cpld
  • Modelsim
  • Complex Programmable Logic Device (Cpld)
  • Microprocessors
  • Lattice
  • Palladium
  • Emulation
  • Uart
  • Hardware Architecture
  • Lec
  • Fpga Prototyping
  • Soc
  • Tcl
  • System on a Chip (Soc)
  • Application-Specific Integrated Circuits (Asic)
  • Fpga
  • Asic
  • Semiconductors
  • Field-Programmable Gate Arrays (Fpga)
  • C
  • Cdc
  • Altera
  • Spi
  • Vhdl
  • Xilinx
  • Systemverilog
  • Lint

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Neeraj Sharma — Senior Principal Application Engineer at Cadence in Austin, TX, US | Unifers