Neeraj Satish
Design & Verification Engineer
- Role
- Design Verification Engineer at UST
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Neeraj Satish
Looking forward for a responsible position in VLSI Domain with a view to utilize and…
Experience
Design Verification Engineer
Oct 2017 — Present · Bengaluru, IN
Education
Christ Nagar English High School, Kowdiar,Trivandrum
Matriculation(SSLC)
1995 — 2005
Christ Nagar English Higher Secondary School
Intermediate
2005 — 2007
Apollo Engineering College, Chennai
Master's Degree
2012 — 2014
P.A. Aziz College of Engineering & Technology
Bachelor’s Degree
2007 — 2011
Skills
- Leadership
- Matlab
- Universal Verification Methodology (Uvm)
- Microsoft Word
- Electronics
- Verilog
- Research
- Functional Verification
- Rtl Design
- Microsoft Office
- Uvm
- Systemverilog
- Project Management
- Linux
- Rtl Coding
- Digital Electronics
- Very-Large-Scale Integration (Vlsi)
- System Verilog
- Microsoft Excel
- Powerpoint
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