Neeraj M.
Lead Engineer @Cadence Design Systems | Physical Design, Timing Analysis, Cutting Edge Technology | Ex - Qualcomm | NSIT
- Role
- Lead Engineer at 铿腾设计系统公司
- Location
- South Delhi, DL, IN
- LinkedIn followers
- 500 followers
About Neeraj M.
ASIC Hardware Design Engineer with a demonstrated history of working in the Semiconductor industry.Contributed to 8+ successful Power, Performance & Area driven Full chip Product tapeouts on cutting edge technology nodes (4nm, 5nm, 7nm, 11nm & 14nm) with tight delivery schedule.Proficient Knowledge in -Shell, TCL scripting, C, Verilog & UNIX operating system.Good understanding of Digital electronics, Digital design, CMOS design, Low power design, Physical Design & Static timing Analysis.Hands on experience in Floorpan, Placement, CTS, Routing, ECO/MECO, Formal verification, Conformal low power checks, Signal integrity analysis, STA & DRC/LVS analysis for Multi-Million gates High performance Subsystem (DDR/Tile).Hands on experience in SoC full chip level PNR execution & sign off on advanced technology nodes 4nm, 5nm).Hands on experience in various technology nodes 4nm, 5nm, 7nm, 11nm (TSMC/Samsung). Tool : Good understanding of Cadence Innovus, Genus, Cadence ispatial, Cerebrus & Fusion compiler. Strong Engineering Professional with a Master of Technology in VLSI Design from Delhi University.
Experience
Lead Engineer
Mar 2024 — Present
Tools: Innovus, Cerebrus and Genus. One Team of the quarter award 2024.Brilliant beginner award 20••••25.Ask Symphony award 2025.
Education
Guru Gobind Singh Indraprastha University
B.tech (ECE), Electronics and Communications Engineering
2012 — 2016
Delhi University
M.tech, Electrical and Electronics Engineering
Netaji Subhas Institute of Technology
M.tech, Integrated Circuit Design
2017 — 2019
Dev Samaj Modern School, Nehru Nagar
School
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