Neeraj I.

About Neeraj I.

Mine work involves set up test benches and implement verification plans using UVM…

Experience

1. Senior Design Verification Engineer

   Analog Devices

   Feb 2025 — Present · Bengaluru, IN

   1)Verification of complex designs such as accelerators/ datapath IP, processor core subsystems, complex interfaces/ protocols such as DDR/ Ethernet/ USB etc using leading edge methodologies like UVM & Formal DV2)Architect the testbench and develop the verification environment in UVM and Formal based verification approaches3)Define testplan, tests and verification methodology for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional coverage. Integrate the block testbench at sub-system level UVM environment and verify integration. Interact with analog co-sim and firmware team in enabling toplevel chip verification aspects3)Package verification environment for Digital IP for seamless integration into verification flow at different stages of execution4)Evaluate 3rd party IPs on key qualitative aspects such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations. Establish evaluation flows for home-grown & 3rd party IPs for consistent benchmarking of DV evaluation5)Build expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D6)Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team

Education

• MEDICAPS INSTITUTE OF TECHNO MANAGEMENT, INDORE

  Bachelor of Engineering - BE, Electrical and Electronics Engineering

• National Institute of Technology, Tiruchirappalli

  Masters of technology, VLSI System