Neelima Chennamaneni
Senior DFT design verification at Apple
- Role
- Senior Dft Design Verification Engineer at Apple
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Neelima Chennamaneni
DFT design verification and architecture for Apple graphics.Design Verification Lead experience in Memory Controller IPs for DDR4/DDR5/LPDDR4/5/HBM DRAM arrays and Graphics (GPU) processor design units. Experienced in architecting large, complex, interconnected testbenches in UVMand building reusable verification IPs, bus-functional models, reference models and DV infrastructure.Lead DV teams to deliver Block IP or SoCs and experience in all DV phases from testplan, coverage plan to System VerilogUVM testbench development, verification reviews, UPF based power aware simulations and Gate Level Simulations andsupporting validation and software teams in early bring up. Adept at collaborating with engineering teams across multipletime-zones and delivering quality results to achieve project goals. Experience in developing project schedules and resolvingresource conflicts.
Experience
Senior Dft Design Verification Engineer
Aug 2022 — Present · Austin, TX, US
Education
Birla Institute of Technology & Science, Pilani
Bachelor's degree, Electrical and Electronics Engineering, Chemical engineering
2002 — 2007
University of Massachusetts Amherst
Master's degree, Electrical, Electronics and Communications Engineering
2007 — 2008
Skills
- C++
- Java
- Verilog
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