Naznin Jahan Afrose
Silicon Packaging Engineering Manager @英特尔
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WORK HISTORY
Silicon Packaging Engineering Manager @英特尔
Chandler, AZ, US
2.5D and 3D Heterogeneous IC Packaging, Semiconductor Packaging and Development, Assembly Test Chip, Design Rule expert, PDK, EDA, EMIB, Interposer, Foveros
EDUCATION
The University of Texas at El Paso
Master of Science (MSc), Mechanical Engineering
Khulna University of Engineering and Technology
Bachelor of Science (B.Sc.), Mechanical Engineering
SKILLS
ABOUT NAZNIN JAHAN AFROSE
Semiconductor Research, 2.5D and 3D IC Packaging, Package Architecture Definition, Chip Package Interactions, EMIB and interposer design, Assembly Test Chip design, IC package design and assembly design rule/design enablement, TD Process Engineering, Failure Mode and Effects Analysis (FMEA), design of experiment techniques (DOE), Statistical Process Control (SPC), Defect analysis and data analysis.
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