Naynesh Shah
Principal Engineer @Ampere
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WORK HISTORY
Principal Engineer @Ampere
San Francisco, CA, US
Brought up and optimized large-scale SoC emulation models on Palladium Z2 for pre-silicon validation. Optimized emulation model capacity and runtime performance by reducing shadow logic and improving critical paths Debugged complex hardware/software interactions in emulation runtime using Verdi, SimVision, and Trace32. Enabled Gate-Level Emulation (GLE) flows to support post-synthesis debug and hardware/software co-verification. Improved runtime throughput by reducing emulation clock stalls and optimizing model performance. Developed automation scripts in Tcl, Python, and Shell to streamline emulation build flows and regression management
EDUCATION
SVCP
Diploma, Industrial Electronics
Savitribai Phule Pune University
B.E, Elecronics and Telecommunication
California State University, Northridge
M.S, Electrical Engineering specialised in field of Digital and Computer Engineering
SKILLS
ABOUT NAYNESH SHAH
Principal Emulation Engineer with 11+ years of experience in pre-silicon emulation and simulation acceleration for large-scale SoC designs. Expertise in bringing up complex designs on Cadence Palladium platforms, optimizing emulation capacity and performance, and debugging hardware/software interactions. Proven ability to deliver scalable emulation environments that accelerate verification closure
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