Navin Navaratnam

About Navin Navaratnam

Senior technical staff with more than 24 years experience in mixed signal and analog VLSI design on FinFET process technologies with extensive exposure and proven track record from product definition, circuit design to post-silicon validation. Solid background in technical leadership and project management, leading technically inclined engineering workforce across multi-cultural and multi-national teams.• Leading pathfinding and execution for low power and high data rate IO for 3D integration • On-Package I/O PHY architect for CPU Client for Multi-Chip Package SOC solution• DDR PHY circuit architect with extensive exposure on post-silicon Bench DV, platform silicon debug and BIOS based memory training algorithm • Strong exposure on Multi-Gigabit serial IOs(Intel’s Quick Path Interface, HDMI), GPIOs(UART, SDIO, I2C, I2S, eMMC), clocking (DLL, Phase Interpolators, clock distribution) and regulators(LVR, LDO)• Profound knowledge of High Speed Low power Digital and Analog design techniques on Intel’s state of the art Intel FinFET CMOS process technology• Extensive familiarity in Cadence tools, Spice based simulators such ADEXL, Parasitic extraction, Reliability/Aging, Monte-Carlo analysis and Static Timing Analysis(STA)• In-depth knowledge of analog system definition, system architecture, simulation and circuit design• Comprehensive knowledge of transistor level circuit tuning & concepts with emphasis on circuit functionality & robustness and strong understanding of analog layout techniques for performance• Strong analytical skill and extensive lab hands-on on silicon debug techniques to identify analog IO circuit and logic issues.• Proficient in C, PERL, UNIX and Python programming languages

Experience

1. Senior Principal Engineer

   Altera

   Jan 2025 — Present

Education

• Universiti Sains Malaysia

  B. Eng, Electrical & Electronics(Microelectronics)

  1995 — 1999

Skills

• Ddr3
• Static Timing Analysis
• Vlsi
• Ddr4
• Microprocessors
• Low-Power Design
• Dll
• Analog Circuit Design
• Mixed Signal
• Processors
• Circuit Design
• Cmos
• Silicon Validation
• Soc
• Lpddr
• Asic
• Dft
• Clocking
• High Speed Serial Io Circuit Design
• Semiconductors
• Analog
• Debugging
• Bench Design Validation & Electrical Validation