Navin Garg
- Role
- Engineering Manager at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Engineering Manager
Mar 2018 — Present · Bengaluru, IN
Tools, flows and methodology team, help reducing turn around time for chip design with quality- Front end flows for SoC development execution- Infrastructure and flows for software development
Skills
- Soc
- Semiconductors
- Eda
- Verilog
- Static Timing Analysis
- Crm
- Asic
- Mixed Signal
- Product Marketing
- Rtl Design
- Clearcase
- Timing Closure
- Physical Design
- Functional Verification
- Tcl
- Vlsi
- Systemverilog
- Debugging
- Ic
- Formal Verification
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