Navin Bhaskar

Experience

1. Silicon Design Engineer

   Google

   Jul 2024 — Present · Bengaluru, IN

   Standard Cell Design Technical Skills Cell Circuit Design: Low Leakage Cells i.e Half Adder,MUX,XOR,XNOR etc. High Speed Cells i.e Half Adder, Full adder, Xor,Xnor,Compressor, Clock Gating Cells, Flops etc. Power Management Cells i.e Retention Flops, Always-On Cells, Always on Latches etc. Retention Level shifters, Level shifters etc-> Spice Simulation i.e Spectre, Monte Carlo, EM/IR analysis, hands-on experience with writing spice decks, analyzing spice simulation results and performing High-Sigma variation analysis-> Understanding of Layout Optimization,Layout Dependent Effects in Finfet/GAA technology->Standard Cell Library Characterization (NLDM,CCS, CCSN,CCSP,EM,LVF liberty view)->Standard Cell Library Validation ->GDS, CDL, ABSTRACT/LEF, Redhawk APL view, Verilog, RTL EDAs views->RTL2GDS Flow i.e Static Timing Analysis (STA) and Synthesis Flow-> Cell Level ATPG Management Skills Technical requirement management : Discuss with customers to finalize project requirements.2. Project management : Project planning, execution and library release.3. Leading: Can lead and mentor a team of 3-4 engineers.

Education

• Indian Institute of Technology (Banaras Hindu University), Varanasi

  M.tech, Electronics Engineering

  2017 — 2019