Naveenkumar Mandla

About Naveenkumar Mandla

Hello! I\'m NaveenKumar Mandla, an Electronics & Communication Engineering graduate with a passion for VLSI design and verification. With a Bachelor\'s degree from G. Pullaiah College of Engineering and Technology and an intermediate from Sri Nandi Jr College, I bring a strong academic foundation and hands-on experience to the table.Skills:HDL: VerilogHVL: System VerilogTB Methodology: UVMVerification Methodologies: Constraint Random Coverage Driven Verification Assertion Based Verification – SVAProtocols: UART,SPI,AHB,APBEDA Tool: Mentor Graphics - Questasim and Xilinx - ISE, Xilinx –VivadoOperating System: LinuxScripting Languages: Perl Scripting, PythonHands on projects:Title: SPI- IP Core – Verificationo Responsibilities: Verified Using UVM testbench and functional coverage.o Description: The UART IP core provides serial communication capabilities, which allow communication with modem or other external devices. UART will operate in three different modes – Simplex mode, Full Duplex mode and loopback mode.o Tool used: Questasim and VCS.Title: Router 1X3 designo Responsibilities: RTL code, verification using Verilog TB o Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves.o Tool used: QuestasimWhy Connect with Me? I am driven by challenges and continuously seek opportunities to learn and grow in the ever-evolving field of VLSI. With a strong work ethic and a collaborative mindset, I thrive in dynamic environments where innovation is valued. Let\'s connect to explore potential collaborations and discuss how I can contribute to your projects or organization.

Experience

1. Design Engineer

   Sevya Multimedia

   Apr 2024 — Present · Hyderabad, IN

Education

• GPCET

  Bachelor of Technology - BTech

  2019 — 2023