Naveena Yadav
Design Verification Engineer at Capgemini
- Role
- Design Verification Engineer at Capgemini Engineering
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Naveena Yadav
Design Verification Engineer with 3 years of relevant experience in ASIC Design and…
Experience
Design Verification Engineer
May 2022 — Present · Bengaluru, IN
Tools: Synopsys, cadence # Experienced in PCIE, AMBA Protocols onsite #Formal verification for 12C, FBIST, UBPC IP Verification onsite#GLS for SOC Verification onsite
Education
Proudadevaraya Institute of Technology, HOSPET
Bachelor of Engineering - BE
2014 — 2018
Ramiaha University
Master of Technology - MTech
2019 — 2021
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