Naveena Gundeti

About Naveena Gundeti

I am a graduate from Portland state university with specialization in Digital IC Design…

Experience

1. Soc Design Engineer

   Intel

   Nov 2018 — Present

   Working for Server Validation Solutions team. As a part of this I support in providing an automated mechanism to configure IP\'s and SoC\'s at high level on the Intel\'s Data Center Chip ->Working in development of new features and Coverage to support Validation Infrastructure->Focus on Integration and Automating Integration of IP’s Design and/or validation environment on an SoC platform along with the automation of connectivity using Python scripting and Magillem IP-XACT Methodology ->Verification of the functionality of IP at boundaries and inter-IP communications on SoC by running suitable tests->Hand\'s on experience in SystemVerilog, constrained randomization, Object Oriented Programming in SV, Intel’s internal tools and GIT Primary Coding languages/Skills: Digital Design & Verification, Systemverilog, Assertions & Constraint randomizations, Python, Object Oriented Programming, OVM and UVM Primary Tools/software: GIT, Unix, Synopsys VCS, Verdi, Magillem, DVT Eclipse

Education

• Sastra University

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2011 — 2015

• Portland State University

  Graduate, Electrical and computers Engineering

  2017 — 2018

Skills

• Windows
• Integrated Circuit Design
• Public Speaking
• System Verilog
• Cmos
• Matlab
• Xilinx
• Programming
• C
• Microsoft Powerpoint
• Linux
• Application-Specific Integrated Circuits (Asic)
• Powerpoint
• Team Leadership
• Rtl Design
• English
• Verilog
• Hardware Engineering
• Testing
• Microsoft Word
• Soc Validation
• Social Media
• Design Validation
• Microprocessors
• Unix
• C++
• Rtl Verification
• Microsoft Excel
• Vlsi Design
• Python
• Microsoft Suites
• Idle
• Systemverilog
• Microsoft Office
• Pl/Sql
• Research
• Sql
• Ic
• Logic Design
• Pcb Design