Naveen Siddesh
senior analog layout enginner at Intel
- Role
- Senior Layout Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Naveen Siddesh
Comprehensive knowledge of designing analog and mixed signal layout,in depth knowledge of VLSI design,standard EDA tools,familiar with cadence and have done critical layouts such as SAR ADC,pipeline ADC,PLL blocks.
Experience
Senior Layout Engineer
Oct 2021 — Present · Bangalore Urban, IN
Education
Cmrit
Master of Technology (MTech), vlsi
2012 — 2014
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