Naveen Seerapu
IP Design Verification Engineer | NITC-M.Tech-VLSI | IIITN-B.Tech-ECE
- Role
- Ip Design Verification Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Naveen Seerapu
Part of the Debug Acceleration team from concurrency domain, owning cross product…
Experience
Ip Design Verification Engineer
Mar 2024 — Present · Bengaluru, IN
Education
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID
Pre University Course(Intermediate)
2011 — 2013
Abhyudaya High School,Bobbili
8th to 10th Class
2008 — 2011
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID
Bachelor of Technology - BTech
2013 — 2017
National Institute of Technology Calicut
Master of Technology - MTech
2018 — 2020
IRIS PUBLIC SCHOOL,Bobbili
2nd to 7th Class
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