Naveen Pantam
MTS Silicon Design Engineer at AMD
- Role
- Mts Silicon Design Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Mts Silicon Design Engineer
Jul 2023 — Present · Hyderabad, IN
Education
Jawaharlal Nehru Technological University, Kakinada
Bachelor of Technology - BTech
2008 — 2012
Skills
- Physical Design
- Static Timing Analysis
- Place & Route
- Cts
- Drc/Lvs
- Primetime
- Icc
- Perl
- Tcl
- Fpga
- Verilog
- Logic Synthesis
- Simulations
- Vivado
- Vhdl
- Zynq
- C Language
- Perl Script
- Unix Shell Scripting
- Can
- Spi
- Iic
- Uart
- Ddr3
- Axi
- C
- Soc
- Asic
- Debugging
- Eda
- Rtl Design
- Field-Programmable Gate Arrays (Fpga)
- System on a Chip (Soc)
- Application-Specific Integrated Circuits (Asic)
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.