Naveen Meduri
Sr Dft Methodology Engineer @NVIDIA
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WORK HISTORY
Sr Dft Methodology Engineer @NVIDIA
US
EDUCATION
Southern Illinois University, Carbondale
Master of Science, Electrical & Computer Engineering
Jawaharlal Nehru Technological University
Bachelor of Technology, Electronics and communications Engineering
SKILLS
ABOUT NAVEEN MEDURI
DFT engineer working on multi-processing, multi-die AI chip Experience in integrating/validating Mentor’s Tessent MBIST and BISR (Built-in Self Repair) in SoC for AI DFT design and validation using Tessent IJTAG, 1687Experience in functional validation including, Analog and Mixed signal circuit validationHands on experience in using VCS, VERDI, Virtuoso, UVM, DVE, revision control with GITDeveloped tester interfacing software classes used for testing Silicon in C++(OOP)Experience in developing/debugging test content for Post-Silicon testing on Advantest ATEProficiency in C, C++, Perl, Python, TCL programmingUnderstanding of SCAN concepts
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