Naveen Kumar Samala
Physical Design Engineer Trainee | VLSI | RTL to GDSII | Fusion Compiler | Training at Maven Silicon.
- Role
- Trainee at Maven Silicon
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Naveen Kumar Samala
Physical Design Engineer | VLSI | ASIC & SOC ImplementationDescription : • Good hands-on experience with EDA Tools like Synopsys (DC, ICC2 & Prime Time) and fusion compiler. • Hands-on experience in complete backend flow - Logical Synthesis, Floor Planning, Placement, Clock Tree Synthesis, Routing, Signoff STA & Physical Verification (DRC & LVS) checks.• Worked on ECO iterations in fixing timing, DRC\'s & generated several automated TCL scriptsSkills -Hard Skills - Physical Design (Floor Planning, Placement, CTS, Routing)- Static Timing Analysis (STA)- Design Rule Checks (DRC) & Layout Verification (LVS)- Digital Electronics & Verilog HDL- TCL Scripting for AutomationEDA Tools - Synopsys – Fusion Compiler, Prime Time (STA), ICC2, Design Compiler- Siemens – Tanner, CaliberSoft Skills:Problem-Solving | Teamwork | Leadership | Time Management
Experience
Trainee
Sep 2024 — Present · Bengaluru, IN
Digital Designing- RTL Designing - Test Bench Designing* Physical Designing- Floor Planning - Placement and Routing- Clock Tree Synthesis- Static Timing Analysis- Physical Verification and Sign-off
Education
Sri Chaitanya College of Education
High School Diploma
2018 — 2020
Matrusri Engineering college
Bachelor of Engineering
2020 — 2024
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