Naveen Kumar S
Graphics -post silicon validation Engineer at intel
- Role
- Graphics -post Silicon Validation Engineer at Intel at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Graphics -post Silicon Validation Engineer at Intel
Jul 2020 — Present · IN
Education
Pes School of Engineering,Bangalore
B.E
2013 — 2017
B. M. S. College of Engineering
Master of Technology - MTech
2018 — 2020
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