Naveen Kumar S
Physical Design Engineer @Google | Ex-Arm | Ex-Intel | VIT’23 - VLSI Design
- Role
- Physical Design Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Naveen Kumar S
Physical Design Engineer with end-to-end experience in two successful tape-outs at advanced nodes — TSMC 3nm (ARM GPU) and Samsung 2nm (ARM CPU). Proficient in hierarchical and flat implementation flows, with expertise in floorplanning, STA, IR drop analysis, and timing/functional ECOs. Passionate on optimizing PPA for complex, next generation designs at advanced technology nodes.
Experience
Physical Design Engineer
Dec 2025 — Present · Bengaluru, IN
Education
Vellore Institute of Technology
Master of Technology - MTech, VLSI Design
Sree Ayyappa Education Centre
SSLC, Secondary Education
2005 — 2015
M. S. RAMAIAH UNIVERSITY OF APPLIED SCIENCES
B.Tech , Electronics and Communications Engineering
2017 — 2021
Vidya Mandir Ind. PU College
Pre-University, PCME
2015 — 2017
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