Naveen Kallanagoudar

About Naveen Kallanagoudar

Working as a ASIC Design Engineer. CAREER SUMMARY• Overall 9 years’ experience as a RTL Design Engineer• Proficient in VHDL and Verilog Languages.• Knowledge on CDC, Linting, ECO, Synthesis and UPF (unified power format).• Tools used like Questa CDC(0-In), Verdi, Spyglass, Design compiler.• Interfaced with ADC, DAC, UART and Keypad.• Interfaced with SRAM, EPROM.• Worked on protocol I2C, SPI, AXI and APB.• Implementation of Ethernet using Tri mode Ethernet MAC IP.• Worked on SOC Designs.• Worked on FPGA Prototyping.• Implemented VME bus protocol to Interface with child Boards.• Implemented ARINC (Aeronautical Radio, Incorporated)717 and CCDL (Cross channel Data Link) protocols.• Interfaced with different types of Encoders using SSI (Synchronous Serial Interface), BiSS (Bidirectional serial synchronous) protocol.Send a Email \"n••••••••@gmail.com\" to Know more.

Experience

1. Senior Staff Engineer

   Qualcomm

   Nov 2025 — Present · Bengaluru, IN

Education

• S.K.S.V.M.A college of Engineering and Technology

  Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering

  2006 — 2010

• B.V.B College of Engineering and Technology

  Master's Degree, VLSI Design and Testing

  2010 — 2012

Skills

• Synthesis
• Linting
• Upf
• Lattice
• Static Timing Analysis
• Soc
• Libero Soc
• Systemverilog
• Vhdl
• Xilinx Ise
• Verilog
• Field-Programmable Gate Arrays (Fpga)
• Fpga
• Asic
• Altera Quartus
• Altera
• Ngspice
• Cdc