Naveen Sidagam

About Naveen Sidagam

I am a result-driven and self-determined Pre-Silicon and Post-Silicon Validation Engineer with a sound knowledge of Computer Architecture, Cache memory, Cache Coherence protocols and nearly 3 years of hands-on experience in meticulously conducting Simulation, Emulation, and Validation of IP-level and SOC-level functionalities. I specialize in ensuring the correctness of the functionality with a keen adherence to Spec and industry design standards, utilizing a diverse range of platforms. I eagerly anticipate the opportunity further to enhance my career. I specialize in server SOC X86, ML XTENSA architectures, ARM architecture, and ZEBU Emulation Platform of System-Level Functional Validation and IP-Level Functional Validation respectively on the multiple IP\'s PCIe(NTB), DSA, and I2C. Good knowledge of NAND and NVMe. Worked on the development of the test cases by understanding the architectures by using the C, and Python languages and having exceptional debugging skills by using the multiple tools in my experience such as JTAG, Trace-32, Verdi-tool, etc. Having a good Knowledge of 3D-NAND memory, DRAM memory and its functional operation, I eagerly anticipate the opportunity to enhance my career.

Experience

1. Engineer

   eInfochips (An Arrow Company)

   Nov 2022 — Present · Bengaluru, IN

   Working on System-Level Functional Validation(SOC) on the server SOC AI XTENSA architecture in the Pre-Silicon Validation environment by developing the functional test cases in Python language and validating it by using the VCS Simulation tool and debugging it by using the Verdi tool.

Education

• Dvr &Dr.Hima sekhar MIC college of technology

  Bachelor of Technology

  2015 — 2019