Navaneeth C P
VLSI Senior Lead CAD Engineer at Qualcomm
- Role
- Senior Lead Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Navaneeth C P
Expert in Static Timing Analysis and Timing Constraints · Expert in Constraint…
Experience
Senior Lead Engineer
Apr 2022 — Present · Bengaluru, IN
Education
RV-VLSI Design Center
Advanced Diploma in ASIC Design
2014 — 2015
Government College Of Engineering Kannur
Bachelor's Degree
2007 — 2011
Manipal Institute of Technology
Master's Degree
2012 — 2014
Kendriya Vidyalaya Payyanur
Plus Two Science Group
2005 — 2007
Skills
- Vlsi
- Xilinx Ise
- Drc
- Tcl
- Synopsys Ic Compiler
- Linux
- Synopsys Design Compiler
- Logic Design
- Physical Design
- Synopsys Primetime
- Static Timing Analysis
- Synopsys Tools
- Software Defined Networking
- Perl
- Application-Specific Integrated Circuits (Asic)
- Vlsi Cad
- Python
- Cmos
- Cadence Virtuoso
- Microelectronics
- Very-Large-Scale Integration (Vlsi)
- Electronics
- Verilog
- Pspice
- Timing Closure
- C++
- Matlab
- Embedded Linux
- Asic
- Questasim
- Lvs
- C
- Programming
- Digital Designs
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