Narveer Yadav
ASIC Engineering Technical Leader
- Role
- Asic Engineering Technical Leader at Cisco
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Asic Engineering Technical Leader
Nov 2024 — Present · Bengaluru, IN
Education
Kurukshetra University
Master of Science - MSc
2007 — 2009
Kurukshetra University
Bachelor of Science - BSc
2004 — 2007
Kurukshetra University
Master of Technology - MTech
2009 — 2011
Yaduvanshi Shiksha Niketan, Mahendergarh
12th CBSE Board
2000 — 2004
Skills
- Low-Power Design
- Place & Route
- Primetime
- Timing
- 45nm
- Static Timing Analysis
- Digital Electronics
- Floorplanning
- Signal Integrity
- Timing Closure
- Verilog
- 16nm
- Integrated Circuit Design
- Drc
- System on a Chip (Soc)
- Physical Design
- Soc
- Cmos
- Asic
- Application-Specific Integrated Circuits (Asic)
- Physical Verification
- Vlsi
- Lvs
- Ic
- Semiconductors
- Tcl
- Digital Ic Design
- Microelectronics
- Very-Large-Scale Integration (Vlsi)
- Clock Tree Synthesis
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