Naresh Kumar Nadipilli

Experience

1. Physical Design Lead

   Intel

   May 2018 — Present · Bengaluru, IN

Education

• National Institute of Technology Karnataka

  M.Tech, VLSI

  2005 — 2007

• Besant

  10th class, SSC

  1996 — 1999

• Vikas Junior College

  12, Maths Physics Chemistry

  1999 — 2001

• Andhra University

  B.E., Electronics and Communication

  2001 — 2005

Skills

• Fpga
• Asic
• Soc
• Emir Analysis
• Timing Closure
• Functional Verification
• Static Timing Analysis
• Integrated Circuit Design
• Primetime
• Vlsi
• Rtl Coding
• Power Analysis
• Physical Design
• Cmos
• Drc
• Eda
• Lvs
• Verilog
• Tcl
• Place & Route