Naresh Vanga
Design Verification Engineer at BITSILICA
- Role
- Design Verification Engineer at BITSILICA
- Location
- Hyderabad, IN
- LinkedIn followers
- 500 followers
About Naresh Vanga
I have knowledge in VLSI and Digital Electronics. Very good at Verilog programming, SV, UVM. Experience in AMBA-APB, AMBA-AXI, PCIE, UCIE Protocols. Involved in defining and driving design and verification methodologies. Work closely with verification leader and development teams to better understand requirements. Good debugging and problem solving skills. Scripting knowledge. Woked for the clients like QUALCOMM and CADENCE.
Experience
Design Verification Engineer
Jul 2021 — Present · Hyderabad, IN
Education
JNTUH College of Engineering Jagityala
Master of Technology - MTech, Digital Systems and Computer Electronics
2015 — 2017
SKIT-JNTUH
Bachelor degree, Electronics and communication engineering
2009 — 2013
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