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Naresh Sambhnani

verification manager in semiconductor.

Role
Verification Manager at 恩智浦半导体
Location
Jaipur, RJ, IN
LinkedIn followers
500 followers
Manufacturing & ProductionView LinkedIn profile

About Naresh Sambhnani

13+ years of experience in VLSI front end verification.Working proficiency on SV, UVM, Verilog, C, C++Knowledge of VHDL, Vera, Perl, Shell scripting.Knowledge of USB3.0 HUB, USB3.0 device,UCHE, Color compression.

Experience

  1. Verification Manager

    恩智浦半导体

    Apr 2023 — Present

Education

  • Birla Institute of Technology and Science, Pilani

    Master of Science (M.S.), Microelectronics

    2013 — 2015

  • University of Rajasthan

    Bachelor of Engineering (BE), Electronics and Communications Engineering

    2004 — 2008

Skills

  • Functional Verification
  • Oop
  • Debugging
  • Fpga
  • Asic
  • Usb3.0
  • Perl
  • Verilog
  • C++
  • Uvm
  • C
  • Unix
  • Shell Scripting
  • Vhdl
  • System Verilog
  • Linux
  • Modelsim
  • Vlsi

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Naresh Sambhnani — Verification Manager at 恩智浦半导体 in Jaipur, RJ, IN | Unifers