Naresh Narayanan
Principal Engineer, Design Verification at Arm
- Role
- Principal Engineer at Arm
- Location
- Raleigh, NC, US
- LinkedIn followers
- 500 followers
About Naresh Narayanan
Design Verification Engineer with extensive experience working on state-of-the-art compute processors for mobile and server markets. Proven technical and leadership skills with a can-do attitude to work past barriers, collaborate across teams and delivery quality products that exceed customer expectations.Specialties: Strong understanding of CPU and memory sub-system architecture. Extensive background in System Verilog, C++, Perl, Python, UVM methodologies and verification infrastructure.
Experience
Principal Engineer
Nov 2025 — Present · Raleigh, NC, US
Verification Lead for ATEG
Education
Texas A&M University
MS, Electrical Engineering
2007 — 2009
Anna University Chennai
B.E, Electrical and Electronics Engineering
2003 — 2007
Skills
- Computer Architecture
- Asic
- Verilog
- Rtl Design
- Logic Design
- Arm Architecture
- Functional Verification
- Perl
- Modelsim
- Static Timing Analysis
- Physical Design
- Debugging
- Spice
- Uvm
- Cadence Virtuoso
- Vlsi
- Systemverilog
- C++
- C
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