Naresh Lakkamraju

About Naresh Lakkamraju

10+ years’ experience in ASIC Physical Design with master’s degree in VLSI Design. Extensive experience on all aspects of physical design including Floor Planning (Hierarchical, Flat, and Block), Power Planning, Partitioning, Placement, Clock Planning and Clock Tree Synthesis, Routing, Complex analog IP integration, Parasitic Extraction, Timing Closure, Static and Dynamic Voltage drop Analysis, Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS, ANT), DFM, DFY and Tapeout. Good Hands-on experience on Implementation of multimillion gate, High performance, and low power SoC designs in cutting edge process technologies like 12nm, 7nm, and 6nm. Developed Flow & Methodology for Cadence-Innovus and Synopsys- IC Compiler II in cutting edge process technologies like 16nm, 12nm, 7nm, and 6nm. Very good experience as a team lead to handle >50M Instance Hierarchical Low Power SOC Designs from Netlist to GDS for WIFI7, Multimedia, Smart Phone applications. Expertise in various physical implementation tools like Synopsys-IC Compiler/IC Compiler II/Cadence- EDI, timing sign-off and ECO generation tools like PT-SI/Tweeker, and physical verification tools like Mentor Graphics- Calibre/ Synopsys-IC validator etc. Successfully done 20+ Tapeouts with first pass silicon success.

Experience

1. Senior Physical Design Engineer

   Google

   Mar 2024 — Present · Bengaluru, IN

Education

• NIT DURGAPUR

  M.TECH

  2009 — 2011

• QIS college of Engg & Tech

  Bachelor of Technology (B.Tech.)

  2004 — 2008