Narendhar Pottavathini
Lead Layout Engineer
- Role
- Lead Layout Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Narendhar Pottavathini
Highly empowered professional with 10 years of experience in Analog and mixed signal…
Experience
Lead Layout Engineer
Dec 2022 — Present · Bengaluru, IN
Education
RV-VLSI Design Centre
ADAD: Advanced Diploma, ASIC Design
2012 — 2013
Trinity Junior College
Intermediate(10+2), Mathematics,Physics,Chemistry
2005 — 2007
ZPHS
S.S.C
2005
Vidya Jyothi Institute Of Technology
B-Tech, Electronics & Comm. Engineering
2007 — 2011
Skills
- Eda
- Layout Design
- Full Custom Ic Layout
- Analog Circuit Design
- Standard Cell
- Linux
- Modelsim
- Physical Design
- Synopsys Primetime
- Verilog
- Asic
- Drc
- Vhdl
- Physical Verification
- Integrated Circuit Design
- Logic Design
- Mentor Graphics - Pyxis
- Logic Synthesis
- Static Timing Analysis
- Synopsys Tools
- Rtl Design
- Lvs
- Cadence
- Pvs
- Pex
- Cadence Virtuoso
- Digital Circuit Design
- Network Theory
- Cmos
- Vlsi
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