Narain Vijayashanker
- Role
- Staff Analog Mixed-signal Design Verification Engineer at Scientific Analog
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Narain Vijayashanker
Electronic design engineer with broad and diverse experience in design, design…
Experience
Staff Analog Mixed-signal Design Verification Engineer
Apr 2023 — Present
Consultant for AMS Design Verification Simulation Tools
Skills
- Pcb Design
- Simulations
- Asic
- Semiconductors
- Python
- Integrated Circuit Design
- Comsol
- C
- Spice
- Maxwell
- Ansys
- Verification and Validation (V&V)
- Network Analyzer
- Algorithms
- Application-Specific Integrated Circuits (Asic)
- Functional Verification
- Solidworks
- Rapid Prototyping
- Finite Element Analysis
- System Architecture
- Verilog
- Verilog-Ams
- Embedded Systems
- Cadence Spectre
- Amperes 3d
- Sensors
- Latex
- Laser Cutting
- Labview
- Cadence Virtuoso
- Matlab
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