Passionate Physical Design Engineer with hands-on experience in ASIC design and implementation.Skilled in floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.Experience with industry-standard EDA tools like Fusion Compiler, Innovus for optimizing power, performance, and area (PPA).Continuous learner, staying updated with the latest
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Nandini N — Silicon Engineering Associate at Accenture in Bengaluru, KA, IN | Unifers