Nandan Roy Avasarala
- Role
- Cerebras
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Nandan Roy Avasarala
Physical Design Engineer- Netlist to GDSII flow Implementation. • Worked on…
Experience
Present
Education
Sri Sathya Sai Higher Secondary School
10th Class
1995 — 2005
Visvesvaraya Technological University
B.E., Telecommunications
2007 — 2011
San José State University
Master's degree, Electrical Engineering [VLSI Design ]
2014
Sri Bhagawan Mahaveer Jain College
2nd PUC, PCME
2005 — 2007
RV-VLSI
PG Diploma, Advanced ASIC Design
2011 — 2012
Skills
- Simulation
- Static Timing Analysis
- Integrated Circuit Design
- Rtl Coding
- Physical Design
- Python
- Cmos
- Physical Verification
- Drc
- Soc
- Asic
- Timing Closure
- Floorplanning
- Modelsim
- Logic Design
- Logic Synthesis
- Lvs
- Digital Design
- Primetime
- Semiconductors
- Xilinx
- Verilog
- Rtl Design
- Custom Design
- Perl
- Vlsi
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.