Working on post-synthesis simulation, parsing VHDL-generated netlists to analyze and compute primitives such as lookup tables, flip-flops, multipliers, adders, and DRAM modules. This process generates accurate output waveforms with just two terminal commands, significantly reducing the overhead of writing testbenches for complex designs and optimizing digital design verification.
Education
Veer Narmad South Gujarat University Vnsgu Surat
Bechlor of Computer Application
2019 — 2022
Dhirubhai Ambani University
Msc, Information Technology
2022 — 2024
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Nandani Sanghani — Systems Development Engineer at Vicharak in Surat, GJ, IN | Unifers