Nalini Sharma

About Nalini Sharma

I\'m excited about the growing advances in the fields of Digital VLSI and always been a keen explorer.experience in Physical Design (RTL-GDSII), worked on 5nm,7nm,10nm (SEC) technology RTL- GDSII implementation. Skills: RTL Design and Simulation using Verilog/VHDL on QuestaSim 10.4c/NCSIM, Logic Synthesis using Xilinx ISE 14.7/Vivado 2018.2 on Artix-7 FPGA Board and using DC Compiler, Timing analysis using PT, Placement and Route, Custom IC Layout and Design on Cadence with PAD analysis (Power*Area*Delay), 7nm HSPICE Simulations, Average Current/Power Graph Design using MATLAB, Programming languages: C/C++ • EDA Tools: IC Compiler, Innovus, Virtuoso, PrimeTime, ModelSim, QuestaSim, Design Compiler and RC Compiler/Genus, Apache RedHawk, Fusion Compiler• Programming languages: C, C++, Verilog, System Verilog, PERL, Python, TCL, Shell scripting.Protocols:PCI-express, ACE, AXI, PCI, UART, MOESIMemory Technologies:DDR(I, II, and SDRAM, SRAM

Experience

1. Senior Physical Design Engineer

   NVIDIA

   Mar 2024 — Present

Education

• University of Southern California

  Masters in Science, Electrical Engineering (VLSI)

  2019

• Vellore Institute of Technology

  B.TECH, Electrical, Electronics and Communications Engineering

  2014 — 2018